1950-102

Data link processor interface

Features

Quad-core 64-bit computing, 1 clock speed, 2.5ghz bus speed, 1333mhz compatible processor socket, lga771 socket cache memory installed size: l2 cache-12mb (2 x 6mb) compatible slots: 1 x processor-lga771 socket

Properties of 1950-102

End Application:
9002389- (3j458) , swan server, slide mt
Part Name Assigned By Controlling Agency:
Inavy-processor, xeon, quad-core e5420
NSN:
5895-01-586-7892
Description:
Processor Interface,data Link
Cage Code:

Definition Data Link Processor Interface

The unit is an intergral part of the surveillance information processing center. It serves as an interface between the test operator position which is a computer workstation and the mission control area network.

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Last modified 11/10/2024